AMD expands AI offensive against Nvidia: Helios system and new Epyc processors announced

Alongside Microsoft, Meta, OpenAI and Oracle, AMD also rolled out a roster of marquee customers planning to deploy Helios in their data centers. Microsoft announced it would integrate the AMD system into its data centers. The list underscores AMD's growing ambition to assert itself in the AI infrastructure market against Nvidia, which, by industry estimates, continues to control more than 95 percent of the data center graphics chip market.

Helios as direct competition to Nvidia

At the center of the processor announcements is the Epyc 9006 family. AMD announced the flagship Epyc 9006X, codenamed Venice-X, aimed at high-performance computing. It uses compute chiplets stacked on top of 3D V-Cache and offers up to 1,152 MB of L3 cache along with 1.6 TB/s of memory bandwidth. For GPU servers, AMD also unveiled the Epyc 9006 LP, codenamed Verano, which targets fast CPU-GPU connectivity and supports LPDDR5X memory similar to Nvidia's Vera CPU.

The Venice generation ships in five variants built around a chiplet architecture and is offered for the SP7 and SP8 sockets. SP8 is designed as a cost-optimized variant with smaller package and IO chiplets; models there ship with 8 to 128 cores across up to four chiplets and eight memory controllers. The top configuration with 256 cores, eight chiplets and 16 memory controllers remains exclusive to the SP7 socket. AMD puts power consumption at up to 600 W for SP7 variants and a maximum of 400 W for SP8 models.

Epyc 9006: five variants on a chiplet foundation

The Venice-HF variant targets Helios GPU blades and delivers 96 Zen 6 cores with up to 5 GHz clocks. It provides 16 memory channels supporting multi-rank DIMMs at speeds up to 12,800 MT/s. AMD highlights that Venice-HF delivers one-third more memory bandwidth than Nvidia's Vera CPU, which AMD pegs at 1.64 TB/s. The Zen 6c chiplets pack 32 cores and are physically larger than the standard Zen 6 chiplets; both variants offer roughly 4 MB of L3 cache per core.

On the GPU roadmap, AMD announced an annual release cadence mirroring Nvidia's. The MI500 series is slated to launch in 2027 and will offer HBM4e memory along with partial optical networking. Shipments of Venice-X and Verano are already scheduled for the second quarter of 2027; a CPU counterpart with Zen 7 cores, codenamed Ferrara, is slated for the MI600 series. The Zen 7 generation (codename Florence) is set to debut in 2028 with AI compute extension matrix instructions, while the Zen 8 family (codename Ravenna) is scheduled for 2030.

GPU roadmap with an annual cadence through 2030

According to AMD's calculations, the upcoming Epyc Venice server CPU platform should deliver roughly 3.3 times the rack throughput of Nvidia's Vera reference system under certain assumptions. This modeled figure serves as a central marketing claim in the rivalry with Nvidia, whose Vera Rubin system is estimated by the Futurum Group, as cited by CNBC, to cost between $3.5 million and $4 million. Bank of America analyst Vivek Arya sees competition around AI infrastructure metrics as a central issue for the industry's future.

An analyst study published by Bank of America argues that Nvidia primarily measures AI infrastructure success by the speed of individual compute steps, while AMD emphasizes the number of AI agents running concurrently per rack. Vivek Arya is sticking with his Buy rating on Nvidia.

Market reaction and analyst assessment

The announcements triggered a clearly asymmetric reaction in the markets. In after-hours trading on NASDAQ, AMD shares rose 1.67 percent to $548.70, while NVIDIA stock edged down 0.37 percent to $207.99. Since the start of 2026, AMD shares have gained roughly 152 percent, while NVIDIA shares are up around 12 percent.